1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device, including a polishing process.
2. Description of the Background Art
In manufacture of a semiconductor device, to realize a fine pattern at the time of forming a plug or a metal line, a step in an under layer on which a predetermined metal film for forming a plug or the like is formed is reduced.
As a method of reducing a step in an under layer, chemical mechanical polishing (hereinafter, simply described as “polishing”) is used. As a conventional semiconductor device manufacturing method, polishing described in Japanese Patent Laying-Open No. 2001-210612 will be described.
First, a metal such as tungsten is deposited on a semiconductor substrate and a predetermined metal pattern is formed by photolithography. An interlayer insulating film is formed on a semiconductor substrate so as to cover the metal pattern.
After that, by photolithography, a plurality of via holes exposing the metal pattern are formed in the interlayer insulation layer. The plurality of via holes are sequentially filled with a barrier film made of titanium or the like and a metal layer made of tungsten or the like.
By performing polishing with a non-selective slurry, the metal layer, barrier layer, and interlayer insulating film are removed and the interlayer insulating film with the flat surface is formed. In each of the plurality of via holes, a via plug of which upper surface is flat is formed. In such a manner, a step in the under layer in the conventional semiconductor device is reduced.
However, the conventional semiconductor device manufacturing method using the polishing has the following problems. The plurality of via plugs are formed in the via holes provided in a predetermined region in the insulating film on the basis of a layout pattern.
At this time, when the polishing process is performed on a region (region A) in which the plurality of via plugs and an insulating film surrounding the via plugs are positioned and a region (region B) in which no via plug is formed and only the insulating film is positioned, the difference (residual step) between the level of the top face of region A and that of the top face of region B after the polishing process occurs depending on pattern density of the via plugs.
Consequently, a problem occurs such that some residual step becomes large to a degree that it cannot be permitted in a photolithography process performed later. The pattern density will be defined later.
When there are a plurality of polishing processes, depending on the residual step which occurs in the first polishing process, there is a case that a residue of a metal film occurs in the step portion in a polishing process performed later. There is consequently the possibility that electric short-circuit occurs via the residue of the metal film.